The Wire · Chips
The silicon beat — GPUs, custom accelerators, HBM, advanced packaging, and the foundries and supply chains that gate every AI buildout.
OpenAI cut GPT-5.6 Luna API prices by 80% to $0.20 per million input tokens and $1.20 per million output, while Terra fell 20% to $2 and $12. Fast mode gives Sol up to 2.5 times Standard speed at twice the price. OpenAI says Sol-assisted kernel work lowered serving cost by 20% and improved token-generation efficiency by more than 15%, while Luna delivers year-old frontier performance at roughly six cents per task-dollar and nearly nine times the speed. The edition connects cheaper models to Amazon's reported $1.8m, 860%-over-budget coding task, Gemini Robotics 2 whole-body control, Nscale's Anyscale acquisition and Okta's roughly $200m Permiso deal.
AMD has posted strong second quarter results and forecast even better future financials once its Helios rack systems and Instinct MI400-series GPUs reach buyers. “In data center AI, the growing number and scale of Helios and MI450-series deployments position the [datacenter] business for significant growth in the second half of the year, with growth accelerating in 2027,” CEO Lisa Su told investors on Tuesday during the chip design company's Q2 earnings call. “We now expect data center segment revenue to more than double year over year in 2027,” she added. Yet, despite reporting Q2 profits surging 163 percent year-over-year on revenues of $11.5 billion, and several multi-gigawatts worth of Helios commitments from the likes of OpenAI, Anthropic, and Meta in the bag, Wall Street isn’t buying it. The company's share plunged 10.5 percent after its results announcement, before settling 8.7 percent below opening price at the time of publication. The apparent cause for concern: AMD's growing exposure to the AI bubble. Much of the company's growth potential across both CPUs and GPUs is tied to AI adoption by a handful of companies that are yet to prove they can operate profitably. On Tuesday's earnings call, Su attempted to assuage investor fears, but in the same breath she said the quiet part out loud. “When we talked about the large frontier-model companies, OpenAI, Anthropic, Meta, they will be consuming through a number of CSPs,” Su said. “There are additional customers or lots of customers who are interested in Helios at, let's call it, a more regular scale than gigawatt scale.” In other words, while AMD can sell plenty of GPUs, most are sold to a handful of customers. And while other entities have AMD on their shopping lists, they don't buy in bulk. Microsoft, another flagship customer for AMD's latest generation of AI picks and shoves, serves both OpenAI and Anthropic, while Meta is reportedly looking to enter the GPU cloud biz itself. Despite this, AMD remains optim
Read full story →AirLLM 70B inference with single 4GB GPU
Read full story →Getting a small local language model running on a notebook or even smartphone in 2026 is trivial. But what about something even smaller and lower-power. Say, like an ESP32 microcontroller that costs less than $10? It might sound impossible — the device is primarily designed for things like remote sensors, IoT, and other embedded applications, not running generative AI models — yet, that's exactly what a developer who goes by the handle SlvDev has managed to do. In a process detailed on GitHub, and recently showcased on the Better Stack YouTube channel, SlvDev documented how he managed to get a small language model running at nearly 10 tokens a second locally on a microcontroller that costs about the same as a fancy cup of coffee. Tiny stories on a tiny microcontroller Cramming a large language model (LLM) onto something as small as a ESP32 microcontroller isn't a trivial task. There's a reason that these models are trained and run on GPUs. LLMs are memory-hungry beasts that typically require between one and four bytes per parameter just to hold their weights in memory. With just 520 KB of SRAM and 8 MB of pseudo SRAM (PSRAM) on the ESP32-S3, you aren't going to be running a model like DeepSeek V4 Flash . To make it work, the dev had to drop the "large" from the language model and settle for something nearly 10,000 times smaller: TinyStories, a 28.9 million-parameter model originally developed by Microsoft Research. However, even this model is asking a lot of an ESP32-S3 module. At 16-bit precision, the model requires about 60 MB of memory that the ESP32 simply doesn't have. So, the dev employed several techniques, some of which we've previously explored, to shrink the model’s footprint. The first is quantization, a process by which weights are compressed by reducing their precision from something like 16-bits of precision to eight, or even four. This enabled SlvDev to trade a bit of accuracy for a 75 percent reduction in memory required. Instead of about 60 MB of me
Read full story →97 points, 16 comments on HN
<p><strong><a href="https://github.com/PipeNetwork/minimax-h3-mlx">PipeNetwork/minimax-h3-mlx</a></strong></p> MiniMax released <a href="https://huggingface.co/MiniMaxAI/MiniMax-H3">MiniMax-H3</a> two days ago - they describe it as a "a general-purpose, omni-modal generative system", which in practice means it accepts text, images, audio and video and can use them to generate up to 15 second video clips with audio included.</p> <p>This Python package ports it to MLX for running on Apple Silicon.</p> <p>I got it running on my M5 Max MacBook Pro. I cloned the repo and ran the model like this:</p> <pre><code># First download the models uvx --from huggingface_hub hf download MiniMaxAI/MiniMax-H3 \ --include 'FL2VA/*' --exclude 'FL2VA/transformer/*' uvx --from huggingface_hub hf download pipenetwork/MiniMax-H3-MLX-8bit # Now run the prompt uv run --with mlx-vlm \ --with-requirements requirements.txt python scripts/generate.py \ "a rainbow colored skunk leaps over a mossy log in a supermarket" \ -o skunk.mp4 \ -c ~/.cache/huggingface/hub/models--MiniMaxAI--MiniMax-H3/snapshots/fa9c8ab1eaa21c8ae25e7e40b83b2e6002f340af/FL2VA \ -t ~/.cache/huggingface/hub/models--pipenetwork--MiniMax-H3-MLX-8bit/snapshots/3ac52081470b0488921c3ec3ba84a39097bf2361 </code></pre> <p>Here's the video I got for the prompt:</p> <blockquote> <p><code>a rainbow colored skunk leaps over a mossy log in a supermarket</code></p> </blockquote> <p><video controls loop preload="none" poster="https://static.simonwillison.net/static/2026/skunk.jpg" width="1344" height="768" style="display: block; width: 100%; height: auto;" > <source src="https://static.simonwillison.net/static/2026/skunk.web.mp4" type="video/mp4"> Your browser does not support HTML5 video. </video> </p> <p>It downloaded ~115 GB of model files, and the video generation took just under 45 minutes.</p> <p>The video is impressive, but the audio is weird speech-like garbage, because I didn't provide any prompt guidance as to what the audio should
As if the graphics card market was not already in a bad state, things are about to get even worse for consumers. The prices for the best graphics cards seems likely to continue to rise, as news of a 20% to 40% increase is now coming out of Japan. CFD Sales Inc., a well-known Japanese technology supplier and distributor, has confirmed these price adjustments for Gigabyte graphics cards. However, given the current times that we live in, the price hikes will likely expand to other brands and make their way to the U.S. market sooner or later. Go deeper with TH Premium: GPUs (Image credit: Noctua) Desktop Roadmap Enterprise Roadmap Rubin in-depth The Stout Owl: The ultimate Noctua G2 PC The revision notice about the Gigabyte graphics card price increases from CFD Sales Inc. reads: "Thank you for your continued support. This is Ogaki from CFD. Thank you for your continued use of CFD-BIZ.com. Due to a price revision by the manufacturer, we will be implementing a price revision (increase) for GIGABYTE VGA products, effective for orders placed from August 1, 2026. The affected products will vary, but we anticipate price revisions of approximately 120% to 140% [editor's note: likely 1.2x or 1.4x] compared to current prices. We sincerely apologize for this sudden announcement, and we appreciate your understanding." There were already early signs that another significant price hike was looming on the horizon. Over the past several weeks, graphics card prices have climbed sharply across Asia in countries like China and South Korea . AI is still gobbling up all the supply for memory chips, and chipmakers are struggling to keep up with that demand. The unprecedented demand for and shift toward AI hardware has substantially impacted the production cost of mainstream graphics cards, and as always, the repercussions pass down to the consumer. One U.S. retailer confirmed to Tom's Hardwar e that it has not received any notice about price adjustments for graphics cards. However, it has
Kioxia and Sandisk used the ongoing Future of Memory and Storage Conference to formally introduce their latest BiCS10 3D QLC NAND device, which features the world's highest areal density and is aimed at high-capacity data center-grade solid-state drives that are meant to maximize storage density in data centers. The new IC comes at the step of Kioxia's and Sandisk's BiCS 3D TLC NAND device that offers an areal density of over 29 Gb/mm 2 . Kioxia's and Sandisk's BiCS10 3D QLC NAND device introduced at FMS features an areal density of 37 Gb/mm 2 , which makes it the world's densest 3D NAND storage device formally introduced to date. The device features 332 active layers as well as an up to 4,800 MT/s interface with a separate command address (SCA) capability, but the manufacturers do not disclose the actual capacity of the IC. Typically, assuming the same number of memory cells and roughly the same die size as the 1Tb BiCS10 3D TLC NAND chip introduced last month, the new memory device should have a capacity of 1.33 Tb, though we are speculating. NAND Layer Counts Sandisk/Kioxia Sandisk/Kioxia Kioxia/Sandisk Samsung Samsung Micron SK hynix YMTC YMTC Generation BiCS10 BiCS10 BiCS 8 V10 V9 Gen 9 (G9) Gen 9 ? Xtacking 3.0/Gen 4 Layers 332-Layer 332-Layer 218-Layer 4xx-Layer 290-Layer (?) 276-Layer 321-Layer 232-Layer 232-Layer Density >37 Gb/mm^2 >29 Gb/mm^2 22.9 Gb mm^2 (?) 28 Gb mm^2 17 Gb mm^2 21.0 Gb mm^2 20 mm^2 >20 Gb mm^2 19.8 Gb mm^2 Architecture QLC TLC QLC TLC TLC TLC TLC TLC QLC Die Capacity ? 1 Tb 2 Tb 1 Tb 1 Tb 1 Tb 1 Tb 1 Tb 1 Tb I/O Speed Up to 4800 MT/s Up to 4800 MT/s Up to 3600 MT/s Up to 5600 MT/s Up to 3200 MT/s Up to 3600 MT/s ? ? ? The new BiCS10 3D QLC NAND flash IC with record storage density is aimed at data center-grade SSDs that must offer both high-capacity and decent performance enabled by high-speed I/O of flash memory. Since such applications also strive to reduce power consumption, Kioxia and Sandisk also implemented their power-isolated l
<p data-block-key="telw2">Makes up a significant proportion of Moonshot's overall compute capacity for Kimi models</p>
<p data-block-key="aqje9">Data center expected to have a total eventual capacity of 15MW</p>
<p data-block-key="8o2zf">Company will deploy GPUs at the Edge</p>
Sandisk and SK hynix on Tuesday formally introduced the High Bandwidth Flash (HBF) specification, their jointly developed storage technology that promises to bring together the non-volatility of 3D NAND and the performance of High Bandwidth Memory (HBM), which will be handy for AI inference systems. The specification was released through the Open Compute Project (OCP), so it will be an open standard rather than a proprietary interface. Tom's Hardware Premium Roadmaps (Image credit: Future) High-Bandwidth Memory (HBM) Roadmap Nvidia Enterprise GPU and CPU Roadmap AI accelerator Roadmap Desktop GPU Roadmap 3D NAND Roadmap The initial specification defines HBF packages with capacities of up to 512GB using either 8-Hi or 16-Hi NAND die stacks, though these will not be standard 3D NAND stacks, but rather specialized devices with a fast interface. In fact, Sandisk once called them HBF core dies rather than 3D NAND die stacks. Performance of HBF is divided into three bandwidth grades ranging from approximately 0.4 TB/s to 3.0 TB/s (though we are not sure whether this figure describes the full HBF subsystem or per-package bandwidth). Such a huge performance range implies that Sandisk and SK hynix expect HBF to have a multi-year roadmap featuring multiple implementations and generations of HBF. It is noteworthy that the most capable implementation of HBF (3 TB/s) is set to beat the memory bandwidth of a single HBM4 memory stack (2 TB/s), though it will be unlikely to beat HBM4 when it comes to latency. (Image credit: SanDisk) Interestingly, SK hynix claims that HBF uses the Universal Chiplet Interconnect Express (UCIe) standard to simplify integration with heterogeneous computing platforms, whereas Sandisk claims that HBF is set to adopt the 'xPU-HBF' interface, which could be its definition of UCIe implemented by companies like Broadcom or Marvell. In addition to capacity and performance targets, the specification establishes electrical and interface characteristics, packag
After the Qwen Exodus last year and new management took over launching more closed model APIs, there was some real doubt as to whether or not this leading open models lab would continue to release relevant models. That doubt is now gone. Qwen 3.8 Max is a MONSTER 2.4T model that would have been the top open model in the world but for the Kimi K3 release we already covered . Qwen offers them on API for $2 input/$6 output per million tokens, but they have promised to open-weight both models. Key Capabilities & Breakthrough Highlights Autonomous Long-Horizon Coding: 10+ Days Unattended Coding: Built a self-evolving coding harness from scratch over a multi-week autonomous run. Autonomous AI Research: Rebuilt a complete paper’s pipeline ( Unified Data Selection for LLM Reasoning ) from scratch, then autonomously ran an iterative research loop over 125 hours to invent a new data selection method beating the original paper’s benchmark by +2.71 points . Competitive Data Science: Competed against 526 human teams in the WWW2025 Multimodal Dialogue Intent Recognition Challenge, placing in the top 13% ( outperforming 87% of human teams ) within 24 hours. Autonomous Hardware & Chip Design: Executed a complete silicon design flow (GCD/RSA cryptographic accelerator) from RTL editing to simulation, synthesis, and physical layout. Reduced gate count from 8,298 to 678 gates while achieving an 81% die area reduction and meeting physical timing closure at 500 MHz. Deep Real-World Work & Operations: Demonstrated production-grade outputs across hundreds of professional workflows (e.g., corporate legal reviews, UI/UX design, structural engineering models, and automated ETF quant research). Outperformed competing models in the E-Commerce Bench (a 365-day store operation simulation), generating a 4.16x return (¥416,252 balance) through continuous game-theoretic negotiation and inventory planning. Multimodal Agents & Visual Feedback: Integrates native visual feedback across planning, coding,
China has changed its legal definition of semiconductors. The National Intellectual Property Administration yesterday issued an expert opinion on recent changes to the regulations governing intellectual property laws as applied to chips. That document, attributed to Guo He, from the School of Intellectual Property at the Renmin University of China, notes that laws in place around the world define integrated circuits as semiconductors. “Today, photonic integrated devices and quantum chip technology are developing rapidly, and optoelectronic chips are already widely used in some fields,” Guo observed, before noting that China’s new rules have replaced references to “semiconductor integrated circuit” with “integrated circuit.” Beijing made that change to include chips that include photonic and quantum elements. “On the surface, this seems insignificant, as various monolithic integrated circuits worldwide still require semiconductor materials as substrates,” Guo wrote, before arguing the significance of the change is that “it demonstrates China's attitude towards intellectual property legislation today: we are no longer conservatives in the intellectual property system.” That may be a little boastful, as the most current international agreement covering chip design is the World Intellectual Property Organization’s Agreement on Trade-Related Aspects of Intellectual Property Rights (TRIP), which describes an integrated circuit as “a product … in which the elements, at least one of which is an active element, and some or all of the interconnections are integrally formed in and/or on a piece of material and which is intended to perform an electronic function.” The Register can imagine that definition extending to optical and quantum elements. The TRIP agreement’s provisions on semiconductors also protect the layout of chips – the proprietary arrangement of elements on a silicon die. That’s an important protection because it takes plenty of time and money to create a layout,
The Helios rackscale system is the culmination of AMD's server hardware, as well as their AI datacenter ambitions. For Advancing AI 2026, the company dove into the architecture of their first rackscale systems, outlining how they have scaled up 72 Instinct MI455X accelerators to act as a single system The post AMD Helios Architecture Deep Dive: The Power of AMD’s Hardware Combined appeared first on ServeTheHome .
Welcome to Import AI, a newsletter about AI research. Import AI runs on arXiv, cappuccinos, and feedback from readers. If you’d like to support this, please subscribe. Subscribe now Self-sustaining and self-replicating AI viruses are here: …Open weight LLMs + a well-designed harness = a persistent, self-sufficient virus… AI researchers have built a prototype computer virus which uses AI models to compromise computers, then uses their underlying GPU resources to run inference, letting it smartly figure out how to infect more hosts. The results were achieved by researchers from the University of Toronto, the Vector Institute, the University of Cambridge, and ServiceNow, and “demonstrate that self-sustaining AI-driven cyber-threats are no longer theoretical.” “We must prepare for autonomous generative adversaries,” they write. “Artificial intelligence (AI) agents enable a fundamentally new threat: a worm that generates tailored attack strategies to each target it encounters. The worm parasitically uses compromised machines to run open-weight large language models (LLMs) to sustain its reasoning, or extend its reach for further attacks”. How it works : “The worm uses stolen computing power from compromised GPU nodes to host LLMs for generative reasoning. It then uses this reasoning to detect vulnerabilities and devise tailored attacks against additional targets, furthering its spread,” they write. “The proof-of-concept operates using only an open-weight LLM running on a single, local GPU, with no reliance on vendor APIs that could be monitored or revoked”. The researchers don’t describe the underlying LLM besides saying it was published in 2025 and can fit on a single A100 GPU with 80GB of VRAM. A successful proof-of-concept via some custom tools : They give the agent a custom harness that comes with built-in helper functions for network discovery, host discovery, foothold exploitation, privilege escalation, privilege escalation exploitation, and tools for replication o
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